Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device performing read and write operations with data transferred through a pair of a bit line and a bit line bar. To be specific, the exemplary embodiments of the present invention relate to a semiconductor memory device which performs a bit line equalization operation by precharging a bit line pair before the data is applied to the bit line pair.
General semiconductor memory devices, including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), include thousands of memory cells for storing data, and store data or output the data according to a command issued from a chipset. In other words, when a chipset requests a write operation, a semiconductor memory device stores data in a memory cell corresponding to an address inputted from the chipset. When the chipset requests a read operation, the semiconductor memory device outputs data from a memory cell corresponding to an address inputted from the chipset. During a write operation, data inputted through an input/output pad is inputted to a memory cell through a data input path, and during a read operation, data is outputted from a memory cell to the exterior through a data output path and an input/output pad.
Meanwhile, a semiconductor memory device includes thousands of memory cells and a set of the memory cells is generally referred to as a memory bank. The number of memory banks inside a semiconductor memory device may be different according to how it is designed. The number of memory banks is on the rise to increase the capacity of a semiconductor memory device.
FIG. 1 illustrates a read operation and a write operation of a conventional semiconductor memory device. Although the semiconductor memory device is designed to have thousands of memory cells inside, the drawing shows one memory cell for the sake of the description herein. The memory cell is labeled with reference numeral ‘110.’
Referring to FIG. 1, a simple read operation performed in a semiconductor memory device will be described hereafter. First, when a word line WL is selected by decoding a row address inputted based upon an active command, a cell transistor T1 of the memory cell 110 is turned on, and data stored in a cell capacitor C1 is charge-shared by a precharged bit line pair BL and /BL. The charge-sharing operation creates a slight potential difference between a bit line BL and a bit line bar /BL. Herein, the cell capacitor C1 is coupled between the cell transistor T1 and a cell plate voltage terminal.
Subsequently, a bit line sense amplifier 120 senses the slight potential difference between the bit line BL and the bit line bar /BL, and amplifies the slight potential difference. In other words, when the potential of the bit line BL is higher than the potential of the bit line bar /BL, the bit line BL is pulled up to a pull-up power source voltage RT0, and the bit line bar /BL is pulled down to a pull-down power source voltage SB. Conversely, when the potential of the bit line BL is lower than the potential of the bit line bar /BL, the bit line BL is pulled down to a pull-down power source voltage SB, and the bit line bar /BL is pulled up to a pull-up power source voltage RT0.
Meanwhile, when a column selection signal YI, selected by decoding a column address inputted based upon a column command signal, is activated, a transistor of a column selector 130 is turned on, and thus, the bit line pair BL and /BL and a segment input/output line pair SI0 and /SI0 are coupled. In other words, a data amplified in the bit line BL is transferred to a segment input/output line SI0, and a data amplified in the bit line bar /BL is transferred to a segment input/output line bar /SI0.
Subsequently, a transistor of an input/output switch 140 is turned on in response to an input/output control signal CTR_I0 corresponding to an active command, and the segment input/output line pair SI0 and /SI0 and local input/output line pair LI0 and /LI0 are coupled. In other words, a data transferred to a segment input/output line SI0 is transferred to a local input/output line LI0, and a data transferred to a segment input/output line bar /SI0 is transferred to a local input/output line bar /LI0. Lastly, a read driver 150 drives a global input/output line GI0 based on the data transferred through the local input/output line pair LI0 and /LI0.
In sum, first the data stored in the memory cell 110 is transferred from the bit line pair BL and /BL to the segment input/output line pair SI0 and /SI0 in response to the column selection signal YI. Then, the data transferred to the segment input/output line pair SI0 and /SI0 is transferred to the local input/output line pair LI0 and /LI0 in response to the input/output control signal CTR_I0. Next, the data transferred to the local input/output line pair LI0 and /LI0 is transferred to the global input/output line GI0. Finally, the transferred data is outputted to the exterior through a corresponding input/output pad (not shown).
Meanwhile, a data applied from the exterior during a write operation is transferred in a direction opposite to the read operation. In other words, a data applied through an input/output pad is transferred from the global input/output line GI0 to the local input/output line pair LI0 and /LI0 through a write driver 160, from the local input/output line pair LI0 and /LI0 to the segment input/output line pair SI0 and /SI0, and from the segment input/output line pair SI0 and /SI0 to the bit line pair BL and /BL. Finally, the data transferred through the path is stored in the corresponding memory cell 110.
The bit line pair BL and /BL is precharged to a precharge voltage VBLP, which is predetermined prior to read and write operations. This operation is performed by a bit line equalizer 170. The bit line equalizer 170 precharges the bit line pair BL and /BL to the precharge voltage VBLP in response to a bit line equalization (BLEQ) signal to thereby equalize the bit line pair. When the BLEQ signal is activated, the precharge voltage VBLP is applied to both the bit line BL and the bit line bar /BL.
A BLEQ signal is generally activated to a voltage level of an external power source voltage VDD, and a transistor of the bit line equalizer 170 is turned on in response to the BLEQ signal. However, the voltage level of the external power source voltage VDD, which is used for the BLEQ signal, has recently been on the decline. Accordingly, it takes a significant amount of time for the transistor of the bit line equalizer 170 to precharge the bit line pair BL and /BL. In order to overcome reduce the time needed to precharge the bit line pair BL and /BL, a power source voltage higher than the external power source voltage VDD is used to drive the BLEQ signal. However, the BLEQ signal having a high voltage level applies a stress to the transistor of the bit line equalizer 170 and causes another concern, which is the occurrence of large leakage current. Therefore, a recent trend is to perform an operation described in FIG. 3 by using a BLEQ signal generator of FIG. 2.
FIG. 2 is a circuit diagram illustrating a circuit for generating a BLEQ signal. Referring to FIG. 2, a BLEQ signal generator drives a BLEQ terminal with a first power source voltage V1 and a second power source voltage V2 in response to a first BLEQ control signal CTR1 and a second BLEQ control signal CTR2. Herein, the first and second BLEQ control signals CTR1 and CTR2 are each activated for a predetermined duration within a precharge duration of a bit line pair BL and /BL prior to read and write operations. The first power source voltage V1 has a voltage level higher than the second power source voltage V2.
FIG. 3 is a timing diagram describing a circuit operation of a BLEQ signal generator shown in FIG. 2. A BLEQ signal is reset to logic low in response to the first and second BLEQ control signals CTR1 and CTR2, while a BLEQ off signal BLEQ_OFF is activated.
Referring to FIG. 3, a word line WL is activated based upon an active command and read and write operations are performed during the duration that the active command is provided. After the word line WL is inactivated, that is, when a precharge operation begins, a BLEQ signal is driven by a first power source voltage V1 as shown by (A) in response to the first BLEQ control signal CTR1. Subsequently, the first BLEQ control signal CTR1 is inactivated and the BLEQ signal is driven by a second power source voltage V2 as shown by (B) in response to the second BLEQ control signal CTR2. Subsequently, before the end of the precharge operation, the BLEQ signal is again driven by the first power source voltage V1 as shown by (C) in response to the first BLEQ control signal CTR1.
Thus, the BLEQ is driven in the method of (A)→(B)→(C) in order to address the above-mentioned concerns. In this method, it is possible to shorten a precharge operation time using a high voltage and to reduce the stress applied to the transistor of the bit line equalizer 170 and the amount of leakage current. In particular, the driving operation of (C) is performed in order to perform a desired equalization operation by stably precharging the bit line pair BL and /BL before the word line WL is re-activated according to the next active operation.
Meanwhile, conventional semiconductor memory devices require a first power source voltage VI corresponding to a high voltage and a second power source voltage V2 corresponding to a low voltage in order to generate a bit line equalization (BLEQ) signal. A power source circuit for generating such power source voltages should be assigned with a relatively large space. Also, a power source line for transmitting a power source should be assigned with a relatively large space as well. Since a power source line applies power noise to adjacent other circuits, the power source line should be disposed carefully. Also, generation of a first BLEQ control signal CTR1 and a second BLEQ control signal CTR2 requires a circuit for generating the first and second BLEQ control signals CTR1 and CTR2 and a timing control circuit for controlling moments when the first and second BLEQ control signals CTR1 and CTR2 are to be activated or inactivated. The additional circuits not only make a semiconductor memory device larger, but also increase the power consumption of the semiconductor memory device.